Embodiments of the present invention relate to the field programmable logic devices, and in particular to high performance memory interfaces.
Programmable devices, such as FPGAs, typically include a programmable device core and one or more input/output (I/O) banks. The programmable device core includes thousands of programmable logic cells that use combinations of logic gates and/or look-up tables to perform logic operations. Programmable devices also include a number of functional blocks having specialized logic devices adapted to specific logic operations, such as adders, multiply and accumulate circuits, phase-locked loops, and one or more embedded memory array blocks. The logic cells and functional blocks are interconnected with a configurable switching circuit. The configurable switching circuit selectively routes connections between the logic cells and functional blocks. By configuring the combination of logic cells, functional blocks, and the switching circuit, a programmable device can be adapted to perform virtually any type of information processing function.
Programmable devices include one or more input/output (I/O) banks for communication with external devices, such as memory devices, network interfaces, data buses and data bus controllers, microprocessors, other programmable devices, ASICs, or any other type of electronic device. Each I/O bank is connected with a number of conductive I/O pins, balls, or other electrical connectors in the programmable device chip package. An I/O bank includes logic for sending and receiving data signals, control signals, clock signals, power and ground signals, or any other type of signal used in conjunction with communications between the programmable device and an external device.
The I/O banks of a programmable device include logic, amplifiers, filters, and other circuits that together can be configured to provide one or more standard interfaces between the programmable device and external devices. Additionally, the I/O banks of a programmable device can be configured to provide custom or proprietary interfaces if required by a particular application.
Double data rate (DDR) memory interfaces are one type of interface that can be implemented with programmable devices. Double data rate interfaces typically provide two bits of data for each clock cycle of a control signal. For example, a double data rate interface can capture or output a first bit on a rising edge of the control signal and capture or output a second bit on the falling edge of the control signal. With this approach, the data is communicated at twice the frequency of the control signal.
The I/O banks of a programmable device include registers for capturing and outputting double data rate signals. These registers typically convert each double data rate input signal into two data signals at the frequency of the data strobe signal and convert two output data signals at the frequency of the data strobe signal into a single double data rate output signal. In previous programmable devices, other functions of the double data rate interface are implemented in the programmable device core using programmable logic cells and other resources. These other functions can include synchronizing input data signals with the clock signal of the programmable device and synchronizing output data signals with the data strobe signal of the double data rate interface.
To perform these functions in the programmable device core of a programmable device, at least a portion of the programmable logic of the programmable device core must operate at the frequency of the data strobe signal of the double data rate interface. For example, for double data rate outputs, the programmable device core must provide data to the registers of the I/O banks at the frequency of the data strobe signal. For double data rate inputs, the registers of the I/O banks provide data to the programmable device core at the frequency of the data strobe signal. Additionally, as timing closure becomes ever more difficult the write data and read datapaths of the memory controller design need to change from operating at the same frequency as the attached DDR or quad data rate (QDR) (or other formats) memory device to a half-rate datapath that operates at half the frequency of the attached memory devices.
As double data rate memory interfaces operate at ever increasing frequencies, it becomes more difficult for the programmable logic resources of the programmable device core to keep pace. For example, the DDR2 memory specifications allow for data rates up to 800 Mbs or more, which corresponds to a control signal frequency of 400 Mhz. DDR3 memory specifications offer higher performance with 600 Mbs to 1.6 Gbs data rate, and QDR and Reduced Latency dynamic random access memory (RLDRAM) operating at 133 MHz to 533 MHz.
Even when programmable logic resources in the programmable device core can operate at sufficient speeds, the memory interface logic in the programmable device core often consumes substantial logic resources and high speed routing connections. As a result, there are less programmable device resources available for implementing the remainder of the design. This makes it more difficult or impossible to implement complicated and/or high speed designs including double data rate interfaces using programmable devices. For example, a 72-bit DDR read and write interface can utilize around 600 programmable device core registers, which can vary depending on configuration.
The core registers used for these functions will introduce timing constraints on other portions of the design, potentially limiting its maximum operating frequency and increasing the amount of time compilation software must process and optimize the design for the programmable device. Additionally, the routing connections between the capture registers in I/O banks and programmable logic resources are relatively long. As a result, these routing connections are often subject to substantial process, voltage, and temperature variations that must be taken into account. These variations and the timing margins required to overcome them often limit the maximum operating frequency of the design implemented with the programmable device.
It is therefore desirable for a programmable device to include I/O blocks optimized for double data rate communications to minimize the required amount of programmable device core logic resources. It is further desirable that the programmable device include I/O blocks with smaller process, voltage, and temperature variations, allowing for larger timing margins and faster operating frequencies. It is also desirable for the programmable device to include I/O blocks that can be flexibly configured to allow for simple integration with a variety of different types of designs, including DDR1-3 and QDRI-II, and RLDRAMI-II, as well as other QDRII variants such as QDRII+ and QDRIII.